Manufacturing Method of Analog Semiconductor Device

专利摘要:
The present invention provides a method for manufacturing an analog semiconductor device capable of minimizing a step between a transistor region and a capacitor region by forming a lower electrode of a capacitor as an impurity diffusion region in an active region. A method of manufacturing an analog semiconductor device according to the present invention is as follows. First, oxygen ions are implanted into a predetermined region of a lower electrode of a capacitor of a semiconductor substrate, high concentration impurity ions are implanted into a predetermined region of the lower electrode so as to be positioned above the oxygen ion, and then heat treatment is performed on the substrate to which the high concentration impurity ions are implanted. At the same time, an oxide film is formed, and a lower electrode of a capacitor including a high concentration impurity diffusion region is formed on the oxide film. After that, a device isolation film is formed on the substrate to define a transistor region and a capacitor region including the oxide film and the lower electrode in an active region between the device isolation films, an insulating film is formed on the entire surface of the substrate, and then on the insulating film. A gate material film is formed. Then, the gate material layer and the insulating layer are patterned to form a gate insulating layer and a gate in the transistor region, and a dielectric layer and an upper electrode are formed on the lower electrode of the capacitor region to form a capacitor.
公开号:KR19990056721A
申请号:KR1019970076732
申请日:1997-12-29
公开日:1999-07-15
发明作者:이재동；차명환
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Manufacturing Method of Analog Semiconductor Device
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an analog semiconductor device capable of minimizing a step between an active region and a capacitor region.
An analog semiconductor device stores data in various states, unlike a digital semiconductor device having two types of data only in a low state and a high state. In addition, a resistor and a capacitor are added to each node required for the circuit in the analog semiconductor element. This capacitor consists of a lower capacitor electrode, an insulating film formed on the lower capacitor electrode, and an upper capacitor electrode formed on the insulating film.
1 is a cross-sectional view showing a conventional analog semiconductor device, with reference to FIG. 1 to explain a manufacturing method thereof.
Referring to FIG. 1, a field oxide film 2 is formed on a semiconductor substrate 1 for isolation between devices, thereby defining a transistor region A in an active region between the field oxide films 2 and a field oxide film. The capacitor region B is defined in the predetermined portion of (2). Then, the gate insulating film 3, the doped first polysilicon film 4, and the tungsten silicide film 5 are sequentially deposited and patterned on the entire surface of the substrate to form the gate 100a in the transistor region A. FIG. In addition, the lower electrode 100b is formed in the capacitor region B. Then, on the lower electrode 100b of the capacitor region B, an upper electrode 9 composed of a polysilicon film 6 for buffer, an oxide film 7 serving as a dielectric film, and a doped second polysilicon film. By forming the capacitor 200 is formed. Here, the buffer polysilicon film 6, when the oxide film 5 is formed directly on the tungsten silicide film 5, the F (fluorin) series of the tungsten silicide film 5 and O ₂ gas during the oxidation process It is formed in order to prevent the reduction of the capacitance of the capacitor caused by the thickness change of the oxide film 7 due to the combination of. Then, the antireflection film 9 is formed on the gate 100a of the transistor region A and on the upper electrode 8 of the capacitor region B.
However, in the conventional analog semiconductor element as described above, as the capacitor 200 is formed on the field oxide film 2, a step is generated between the transistor region A and the capacitor region B. FIG. Although the planarization process is performed to reduce such a step, the planarization of the surface is not completely performed, which causes not only disconnection of the wiring when the metal wiring is formed, but also causes problems such as notching in the photolithography process. Decreases the reliability and yield. In addition, this problem appears even more deadly in sub-micron devices.
Accordingly, the present invention has been made to solve the above-described problems, and by forming a transistor and a capacitor in the active region, and forming a lower electrode of the capacitor as an impurity diffusion region in the active region, the step between the transistor region and the capacitor region is reduced. It is an object of the present invention to provide a method for manufacturing an analog semiconductor device that can be minimized.
1 is a cross-sectional view showing a conventional analog semiconductor device.
2A to 2C are cross-sectional views illustrating a method of manufacturing an analog semiconductor device according to an embodiment of the present invention.
[Description of Code for Major Parts of Drawing]
21 semiconductor substrate 22 mask pattern
23: oxygen ion 23a: oxide film
24: high concentration n-type impurity ion 24a: lower electrode
25 device isolation layer 26a gate insulating film
26b: dielectric film 27: doped polysilicon film
28: tungsten silicide film 29: antireflection film
300a: gate 300b: upper electrode
400: capacitor A: transistor region
B: capacitor area
Method for manufacturing an analog semiconductor device according to the present invention for achieving the above object is as follows. First, oxygen ions are implanted into a predetermined region of a lower electrode of a capacitor of a semiconductor substrate, high concentration impurity ions are implanted into a predetermined region of the lower electrode so as to be positioned above the oxygen ion, and then heat treatment is performed on the substrate to which the high concentration impurity ions are implanted. At the same time, an oxide film is formed, and a lower electrode of a capacitor including a high concentration impurity diffusion region is formed on the oxide film. After that, a device isolation film is formed on the substrate to define a transistor region and a capacitor region including the oxide film and the lower electrode in an active region between the device isolation films, an insulating film is formed on the entire surface of the substrate, and then on the insulating film. A gate material film is formed. Then, the gate material layer and the insulating layer are patterned to form a gate insulating layer and a gate in the transistor region, and a dielectric layer and an upper electrode are formed on the lower electrode of the capacitor region to form a capacitor.
Here, the oxygen ions are ion implanted two to three times by varying the ion implantation energy, the heat treatment is carried out at a high temperature of about 900 to 1,100 ℃.
According to the present invention described above, by forming a transistor and a capacitor in the active region, by forming a lower electrode of the capacitor in the active region with a high concentration impurity diffusion region, it is possible to significantly reduce the step between the transistor region and the capacitor region. As a result, since the planarization of the surface is easily performed, not only the disconnection problem of the wiring when forming the metal wiring is prevented, but also the problem such as notching during the photolithography process is prevented, thereby improving the reliability and yield of the device.
(Example)
Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
2A to 2C are cross-sectional views illustrating a method of manufacturing an analog semiconductor device according to an embodiment of the present invention.
Referring to FIG. 2A, a photosensitive film is coated on a p-type semiconductor substrate 21 including silicon, exposed and developed by photolithography to form a mask pattern 22 exposing a predetermined region of the lower electrode of the capacitor. Then, ion implantation of oxygen ions 23 with high energy into the exposed lower electrode predetermined region, wherein the ion implantation is performed by varying the energy so as to have a gentle doping profile according to a desired thickness. Proceed in turn. Subsequently, the high concentration n-type impurity ions 24 are implanted into the exposed lower electrode predetermined region to be positioned on the oxygen ion 23.
Referring to FIG. 2B, the mask pattern 22 is removed by a known method, and heat treatment is performed at a high temperature of about 900 to 1,100 ° C. Accordingly, the oxygen ion 23 reacts with silicon to form the oxide film 23a, and the high concentration n-type impurity ions 24 are activated to form a high concentration n-type impurity diffusion region on the substrate surface on the oxide film 23a. The lower electrode 24a is formed. Here, the oxide film 23a electrically insulates the lower electrode 24a from the substrate 21, thereby preventing generation of parasitic currents caused by the junction capacitor. That is, when the lower electrode 24a and the substrate 21 have the same potential, the junction capacitor does not affect the analog capacitor. However, when the lower electrode 24a and the substrate 21 have the same potential, the junction capacitor affects the analog capacitor. 23a is formed.
Then, the device isolation film 25 is formed on the substrate 21 by using a well-known trench device isolation technique, and the transistor region A and the capacitor region B are respectively formed in the active region between the device isolation films 25. define. Here, the capacitor region B is a region including the oxide film 23a and the lower electrode 24a. Then, although not shown, ion implantation for well and threshold voltage control is performed.
Referring to FIG. 2C, an insulating film is formed over the entire surface of the substrate, a polysilicon film doped as a gate material film and a tungsten silicide film are sequentially formed on the insulating film, and an anti-reflection film is formed thereon. Then, the antireflection film, the tungsten silicide film, the polysilicon film, and the insulating film are patterned to include the gate insulating film 26a in the transistor region A and the antireflection film 29 on the upper portion, and the polysilicon film 27 And a tungsten silicide film 28 is formed. At the same time, the capacitor region B is provided with a dielectric film 26b and an antireflection film 29 thereon, and a capacitor is formed by forming an upper electrode 300b made of a polysilicon film 27 and a tungsten silicide film 28. To form 400.
Then, although not shown, a subsequent process is carried out by a known method to complete the transistor in the transistor region A. FIG.
On the other hand, in the above embodiment, the gate insulating film and the dielectric film are formed to have the same thickness, but when the thickness of the dielectric film is formed to be thicker, although not shown, the capacitor is formed after the first insulating film having the gate insulating film thickness is formed on the entire surface of the substrate. The second insulating film is selectively formed only in the region, so that the thickness of the insulating layer between the capacitor region and the transistor region is different.
According to the present invention described above, by forming a transistor and a capacitor in the active region, by forming a lower electrode of the capacitor in the active region with a high concentration impurity diffusion region, it is possible to significantly reduce the step between the transistor region and the capacitor region. As a result, since the planarization of the surface is easily performed, not only the disconnection problem of the wiring when forming the metal wiring is prevented, but also the problem such as notching during the photolithography process is prevented, thereby improving the reliability and yield of the device.
In addition, since the deposition process of the polysilicon film for forming the lower electrode of the capacitor is excluded, and the gate insulating film and the dielectric film can be formed at the same time, there is an effect of simplifying the process, and an oxide film under the high concentration junction region serving as the lower electrode of the capacitor. By forming the capacitor, it is possible to maintain the same capacitor characteristics when the lower electrode is formed on the field oxide film as in the prior art. In addition, in the present invention described above, since the lower electrode process of the capacitor is first performed before the transistor is manufactured, the characteristics of the transistor are not affected.
In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

权利要求:
Claims (8)
[1" claim-type="Currently amended] Injecting oxygen ions into a predetermined region of the lower electrode of the capacitor of the semiconductor substrate;
Implanting high concentration impurity ions into the predetermined region of the lower electrode to be positioned above the oxygen ion;
Heat treating the substrate into which the high concentration impurity ions are implanted to form an oxide film, and simultaneously forming a lower electrode of a capacitor including a high concentration impurity diffusion region on the oxide film;
Forming an isolation layer on the substrate to define a transistor region in the active region between the isolation layer and a capacitor region including the oxide layer and the lower electrode;
Forming an insulating film on the entire surface of the substrate;
Forming a gate material film on the insulating film; And,
Patterning the gate material film and the insulating film to form a gate insulating film and a gate in the transistor region, and simultaneously forming a dielectric film and an upper electrode on the lower electrode of the capacitor region to form a capacitor. An analog semiconductor device manufacturing method.
[2" claim-type="Currently amended] The method of claim 1, wherein the implanting of oxygen ions comprises ion implantation two to three times with different ion implantation energies.
[3" claim-type="Currently amended] The method of claim 1, wherein the heat treatment is performed at a high temperature of about 900 to 1,100 ℃.
[4" claim-type="Currently amended] The method of claim 1, wherein the device isolation layer is formed by a trench device isolation technology.
[5" claim-type="Currently amended] The method of claim 1, further comprising forming a well and adjusting a threshold voltage between forming the device isolation layer and forming the insulating layer.
[6" claim-type="Currently amended] The method of claim 1, wherein the gate material layer is formed by sequentially stacking a doped polysilicon layer and a tungsten silicide layer.
[7" claim-type="Currently amended] The method of claim 1, wherein the forming of the gate material layer comprises forming an anti-reflection film on the gate material layer.
[8" claim-type="Currently amended] The method of claim 1, wherein forming the insulating film when the thicknesses of the dielectric film and the gate insulating film are different.
Forming a first insulating film having a thickness of the gate insulating film on the entire surface of the substrate; And,
And selectively forming a second insulating film on the first insulating film of the capacitor region.

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同族专利:

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公开号 | 公开日

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US6215142B1|2001-04-10|

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KR100258203B1|2000-06-01|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1997-12-29|Application filed by 김영환, 현대전자산업 주식회사

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1997-12-29|Priority to KR1019970076732A

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1999-07-15|Publication of KR19990056721A

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2000-06-01|Application granted

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2000-06-01|Publication of KR100258203B1

优先权:

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申请号 | 申请日 | 专利标题

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KR1019970076732A|KR100258203B1|1997-12-29|1997-12-29|Method for manufacturing analog semiconductor device|